Your model. Your hardware.
We convert your existing AI models to run on FPGAs at a fraction of the power—no retraining, no new hardware, no GPU dependency. How we work on type1compute.com →
Currently engaged with tier 1 defense primes and international systems integrators.
01 / Open source
Documentation in this site matches the open-source lineup featured on type1compute.com. Each project is also listed on our GitHub organization, with a mirrored build at GitHub Pages docs.
Neuromorphic intermediate representation for Type 1 Compute hardware. SDK with PyTorch bridge, HDF5 serialization, and visualization—export models without owning every hardware detail.
Unsupervised satellite detection from asynchronous event streams. Three-layer spiking convolutional network trained with STDP—built for space domain awareness.
Detects and classifies 11 radar signal types from spectrograms in real time. ResNet-18 backbone on a modified YOLO-style architecture for RF workloads.
End-to-end pipeline for real-time object detection and tracking on event camera data. BICLab ECCV 2024 lineage with ByteTracker for temporal continuity.
Benchmark
Gesture recognition benchmark (DVS128 dataset)
Energy efficiency on neuromorphic-emulated FPGA hardware. Gesture recognition PDF brief →
244× more efficient than CPU, 9.5× more efficient than Jetson
02 / Research
Technical results across sparse inference, event-driven perception, and autonomous edge compute—additional medical and industrial applications available on request.
SpikeYOLO: track fast-moving threats in real time using far less power than conventional AI stacks.
Open PDF brief →
Energy efficiency measured on neuromorphic-emulated FPGA hardware vs. edge GPUs and CPUs.
Open PDF brief →
Low-SWaP inference for platforms where every watt counts.
Open PDF brief →
Deterministic, low-latency inference for harsh environments.
Open PDF brief →03 / Process
Full process narrative on type1compute.com →
Hand us your PyTorch or ONNX model as-is. No retraining. No pipeline changes. Your training workflow stays the same.
We handle conversion, optimization, and FPGA deployment. Your team works with the outcome—no HDL expertise required on your side.
We maintain the deployment after handoff. Optimization continues as your workload evolves.
On the roadmap: custom ASIC, 100× efficiency over Jetson, priority access for pipeline partners.
04 / Contact
Contact, backers, and apply on type1compute.com →
SWaP-constrained platforms, autonomous systems, EW, radiation-tolerant compute.
5G baseband, RF classification, sparse signal processing on FPGAs.
Vibration, acoustic, and thermal sensor fusion at the edge.
EEG, EMG, and implantable-device inference—defining the problem together.
support@type1compute.com · We respond within 48 hours.